A Pipelined Noise-Shaping SAR ADC Using Ring Amplifier

In this study, a pipelined noise-shaping successive-approximation register analog-to-digital converter (PLNS-SAR ADC) structure was proposed to achieve high resolution and be free from comparator design requirements. The inter-stage amplifier integrator of the PLNS-SAR ADC were implemented through ring with gain speed. designed improve power efficiency tolerant process–voltage–temperature (PVT) variation, uses single loop common-mode feedback (CMFB) circuit. By processing residual signals amplifier, can maximized, low-power system 30% lower consumption than that conventional is implemented. With high-gain noise leakage greatly suppressed, mismatches between analog digital correction filters. measured signal distortion ratio (SNDR) 70 dB for 5.15 MHz bandwidth (BW) at 72 MS/s sampling rate (Fs) an oversampling (OSR) 7, 2.4 mW. FoMS,SNDR (= SNDR + 10log10BW/Power) 163.5 dB. in study wide BW good efficiency, without filter calibration process, use ADC.